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| N-CHANNEL 100V - 0.019 - 80A DPAK/TO-220 STripFETTM II POWER MOSFET Table 1: General Features TYPE STB60NF10 STP60NF10 STB60NF10 STP60NF10 Figure 1:Package RDS(on) ID 80 A 80 A VDSS 100 V 100 V < 0.023 < 0.023 TYPICAL RDS(on) = 0.019 EXTREMELY HIGHL dv/dt CAPABILITY 100% AVALANCHE TESTED SURFACE-MOUNTING DPAK (TO-263) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4") 3 1 3 1 2 DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFETTM process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. APPLICATIONS HIGH EFFICIENCY DC/DC CONVERTERS, INDUSTRIAL, AND LIGHTING EQUIPMENT. MOTOR CONTROL D2PAK TO-263 (Suffix "T4") TO-220 Figure 2: Internal Schematic Diagram Table 2: Ordering Information SALES TYPE STB60NF10T4 STP60NF10 MARKING B60NF10 P60NF10 PACKAGE TO-263 TO-220 PACKAGING TAPE & REEL TUBE Table 3:ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(*) ID IDM(*) Ptot dv/dt (1) EAS (2) Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Value 100 100 20 80 66 320 300 2 16 485 -55 to 175 Unit V V V A A A W W/C V/ns mJ C (*) Pulse width limited by safe operating area. (**) Current Limited by Package (1) ISD 80A, di/dt 300A/s, VDD V(BR)DSS, Tj TJMAX (2) Starting Tj = 25 oC, ID = 40A, VDD = 30V May 2005 Rev. 2.0 1/10 STB60NF10 STP60NF10 Table 4: THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 0.5 62.5 300 C/W C/W C ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) Table 5: OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 20 V Min. 100 1 10 100 Typ. Max. Unit V A A nA Table 6: ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V ID = 250 A ID = 40 A Min. 2 Typ. 3 0.019 Max. 4 0.023 Unit V Table 7: DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 25 V ID = 40 A Min. Typ. 78 4270 470 140 Max. Unit S pF pF pF VDS = 25V f = 1 MHz VGS = 0 2/10 STB60NF10 STP60NF10 ELECTRICAL CHARACTERISTICS (continued) Table 8: SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50 V ID = 40 A VGS = 10 V RG = 4.7 (Resistive Load, Figure ) VDD= 50V ID= 80A VGS= 10V Min. Typ. 17 56 104 20 32 Max. Unit ns ns nC nC nC Table 9: SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 50 V ID = 40 A VGS = 10 V RG = 4.7, (Resistive Load, Figure 3) Min. Typ. 82 23 Max. Unit ns ns Table 10: SOURCE DRAIN DIODE Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A VGS = 0 92 340 7.4 Test Conditions Min. Typ. Max. 80 320 1.3 Unit A A V ns C A ISD = 80 A di/dt = 100A/s Tj = 150C VDD = 50 V (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area. Figure 3: Safe Operating Area Figure 4: Thermal Impedance 3/10 STB60NF10 STP60NF10 Figure 5: Output Characteristics Figure 6: Transfer Characteristics Figure 7: Transconductance Figure 8: Static Drain-source On Resistance Figure 9: Gate Charge vs Gate-source Voltage Figure 10: Capacitance Variations 4/10 STB60NF10 STP60NF10 Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 12: Normalized on Resistance vs Temperature Figure 13: Source-drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature. . . . . 5/10 STB60NF10 STP60NF10 Figure 15: Unclamped Inductive Load Test Circuit Figure 16: Unclamped Inductive Waveform Figure 17: Switching Times Test Circuits For Resis- tive Load Figure 18: Gate Charge test Circuit Figure 19: Test Circuit For Inductive Load Switch- ing And Diode Recovery Times 6/10 STB60NF10 STP60NF10 D2PAK MECHANICAL DATA DIM. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 8 0 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.591 0.050 0.055 0.094 0.015 8 mm. MIN. 4.4 2.49 0.03 0.7 1.14 0.45 1.21 8.95 8 10.4 0.394 0.334 0.208 0.624 0.055 0.069 0.126 TYP. MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.028 0.045 0.018 0.048 0.352 0.315 0.409 inch. TYP. TYP. 0.181 0.106 0.009 0.037 0.067 0.024 0.054 0.368 7/10 STB60NF10 STP60NF10 TO-220 MECHANICAL DATA DIM. A C D E F F1 F2 G G1 H2 L2 L3 L4 L5 L6 L7 L9 DIA 13 2.65 15.25 6.20 3.50 3.75 mm. MIN. 4.4 1.23 2.40 0.49 0.61 1.14 1.14 4.95 2.40 10 16.40 28.90 14 2.95 15.75 6.60 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 TYP. MAX. 4.6 1.32 2.72 0.70 0.88 1.70 1.70 5.15 2.70 10.40 MIN. 0.173 0.048 0.094 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 1.137 0.551 0.116 0.620 0.260 0.154 0.151 inch. TYP. TYP. 0.181 0.051 0.107 0.027 0.034 0.067 0.067 0.203 0.106 0.409 8/10 STB60NF10 STP60NF10 Table 11:Revision History Date May 2005 May 2005 Revision 1.0 2.0 FIRST ISSUE Description of Changes ADDED PACKAGE DPAK 9/10 STB60NF10 STP60NF10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America. www.st.com 10/10 |
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